Method and apparatus for a fully differential amplifier output stage

ABSTRACT

The input stage of the fully differential amplifier output stage is configured in a differential pair configuration with a tail current. The tail current is divided between two legs of the input stage and is higher in the leg that has the higher of the two input voltage levels (in or inb). The devices in each leg of the fully differential amplifier output stage may be cascoded to avoid electrical voltage overstress. The top device in each leg of the differential input stage may be coupled in a diode configuration and is utilized to mirror the current into another NMOS current mirror as well as to a PMOS output device. The gate of the PMOS output devices are connected in a cross-coupled configuration. The NMOS current mirrors are utilized to mirror the current into the NMOS output devices in a non-cross-coupled configuration.

CROSS-REFERENCE TO RELATED APPLICATIONS/INCORPORATION BY REFERENCE

This application makes reference, claims priority to, and claims the benefit of United States Provisional application Ser. No. ______ (Attorney Docket No. 15904US01) filed Jul. 23, 2004.

The above stated application is hereby incorporated herein by reference in its entirety.

FIELD OF THE INVENTION

Certain embodiments of the invention relate to differential amplifiers. More specifically, certain embodiments of the invention relate to a method and apparatus for a fully differential amplifier output stage.

BACKGROUND OF THE INVENTION

A transistor is an electronic device that permits current flow in electronic circuits. In this regard, the transistor permits the current to flow in a controlled manner whenever an electronic circuit attempts to push current through the transistor. In this manner, the transistor generically operates as a regulator or valve, which regulates the flow of current.

In order to mitigate the effects of impairments such as noise, transistors may be arranged so that they form a differential amplifier. Differential amplifiers form the basis of operational amplifiers, the latter of which are generally referred to as op amps. Differential amplifiers are electronic circuits, which are designed with an internal symmetry that is configured to cancel errors that are shared by both sides of the differential amplifier. These errors may include internal or external errors. Internal errors may include temperature changes, which in certain instances may affect both sides of the operational amplifier to approximately the same degree. Transistor mismatch is another example of an internal error. Whenever both sides are affected to approximately the same degree, a nulling or canceling effect occurs. External errors may include noise picked up by inputs of the differential amplifier. In this regard, the differential amplifier may be adapted to eliminate common mode noise. Furthermore, the differential amplifier may require that the signal appear as a difference between waveforms occurring on either side of the differential amplifier. Accordingly, the differential amplifier may be configured to reject certain signal components such as noise and amplify desired signal components.

Some conventional differential amplifiers require a reference voltage or reference current in order for the differential amplifier to operate properly. Additionally, some differential amplifier designs utilize large numbers of transistors. In general, the greater the number of transistor devices, the greater the number of operating variables that will vary with respect to each of the sides of a differential amplifier. Consequently, differential amplifiers that utilize a large number of transistors may be more difficult to control and tune, and may also be less predictable with respect to process or operating variations. Furthermore, most conventional analog differential amplifiers are generally adapted to take a relatively small differential input voltage and produce as an output a voltage having a larger magnitude. These conventional analog differential amplifiers are usually optimized to operate in a specified voltage range and may not function at all if operated outside that range.

Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.

BRIEF SUMMARY OF THE INVENTION

Aspects of the invention may provide a system and method for a fully differential amplifier output stage. In one system embodiment of the invention, a transistor circuit may include an input stage, a first output stage and a second output stage. The input stage may comprise a first current source coupled to a first transistor, a second transistor coupled to the first transistor, where the second transistor may be configured as a current mirror. A third transistor may be coupled to the first current source, and a fourth transistor may be coupled to the third transistor, where the fourth transistor may be configured as a current mirror.

The first output stage may comprise a fifth transistor coupled to the second transistor and a sixth transistor coupled to the fifth transistor, where the sixth transistor may be configured as a current mirror. A seventh transistor may be coupled to the sixth transistor and an eighth transistor may be coupled to the seventh transistor. The a tenth transistor coupled to the ninth transistor, where the tenth transistor may be configured as a current mirror. The eleventh transistor may be coupled to the tenth transistor, and a twelfth transistor may be coupled to the eleventh transistor.

A first input may be coupled to a gate of the first transistor and a second input may be coupled to a gate of the third transistor. A first output may be coupled to a drain of the twelfth transistor and a drain of the eleventh transistor, and a second output may be coupled to a drain of the eighth transistor and to a drain of seventh transistor. In addition, the second transistor may be coupled to the twelfth transistor and the fourth transistor may be coupled to the eighth transistor. The first input and the second input may be complementary inputs and the first output and the second output may be complementary outputs. In addition, a higher voltage potential of an external power source may be coupled to a source of each of the second transistor, the fourth transistor, the fifth transistor, the eighth transistor, the ninth transistor, and the twelfth transistor, all of which may be PMOS transistors. A lower voltage potential of an external power source may be coupled to a source of each of the sixth transistor, the seventh transistor, the tenth transistor, the eleventh transistor and the first current source. The first transistor, the third transistor, the sixth transistor, the seventh transistor, the tenth transistor, the eleventh transistor and the first current source may be NMOS transistors.

A drain of the first current source may be coupled to a source of the first transistor and to a source of the third transistor. A first terminal of a first resistive device may be coupled to a drain of the first current source and a second terminal of the first resistive device may be coupled to a source of the first transistor and to a source of the third transistor. A gate of the second transistor may be coupled to a drain of the second transistor, to a drain of the first transistor, to a gate of the fifth transistor, and to a gate of the twelfth transistor. A first terminal of a second resistive device may be coupled to a gate of the second transistor, to a drain of the second transistor, to a drain of the first transistor, and to a gate of the fifth transistor and the second terminal of the second resistive device may be coupled to a gate of the twelfth transistor. A gate of the fourth transistor may be coupled to a drain of the fourth transistor, to a drain of the third transistor, to a gate of the ninth transistor, and to a gate of the eighth transistor.

In addition, a first terminal of a third resistive device may be coupled to a gate of the fourth transistor, to a drain of the fourth transistor, to a drain of the third transistor, and to a gate of the ninth transistor. The second terminal of the third resistive device may be coupled to a gate of the eighth transistor. A gate of the sixth transistor may be coupled to a drain of the sixth transistor, to a drain of the fifth transistor, and to a gate of the seventh transistor. A gate of the tenth transistor may be coupled to a drain of the tenth transistor, to a drain of the ninth transistor, and to a gate of the eleventh transistor.

A first pull-down device, which may be a NMOS transistor, may be coupled to the sixth transistor and the seventh transistor. A lower voltage potential of an external power source may be coupled to a source of the first pull-down device, and a drain of the first pull-down device may be coupled to a gate of the sixth transistor and to a gate of the seventh transistor. A second pull-down device, which may be a NMOS transistor, may be coupled to a tenth transistor and to an eleventh transistor. A lower voltage potential of the external power source may be coupled to a source of the second pull-down device, and a drain of the second pull-down device may be coupled to a gate of the tenth transistor and to a gate of the eleventh transistor.

A first pull-up device, which may be a PMOS transistor, may be coupled to the fourth transistor, the eighth transistor, and the ninth transistor. A higher voltage potential of the external power source may be coupled to a source of the first pull-up device. A drain of the first pull-up device may be coupled to a gate of the fourth transistor, to a drain of the fourth transistor, to a gate of the eighth transistor and to a gate of the ninth transistor. In an alternate embodiment, a higher voltage potential of the external power source may be coupled to a source of the first pull-up device, which may be a PMOS transistor. A drain of the first pull-up device may be coupled to a gate of the eighth transistor and to a first terminal of a third resistive device. The second terminal of the third resistive device may be coupled to a gate of the fourth transistor, to a drain of the fourth resistor, and to a gate of the ninth transistor.

A second pull-up device, which may be a PMOS transistor, may be coupled to the second transistor, to the fifth transistor and to the twelfth transistor. A higher voltage potential of the external power source may be coupled to a source of the second pull-up device. A drain of the second pull-up device may be coupled to a gate of the second transistor, to a drain of the second transistor to a gate of the fifth transistor and to a gate of the twelfth transistor. In another embodiment, a higher voltage potential of the external power source may be coupled to a source of the second pull-up device, which may be a PMOS. A drain of the second pull-up device may be coupled to a gate of the twelfth transistor and to a first terminal of a second resistive device. A second terminal of the second resistive device may be coupled to a gate of the second transistor, to a drain of the second transistor and to a gate of the fifth transistor.

In accordance with another embodiment of the invention, at least one transistor may be coupled between the first transistor and the second transistor in a cascode arrangement. At least one transistor may be coupled between the third transistor and the fourth transistor in a cascode arrangement and at least one transistor may be coupled between the fifth transistor and the sixth transistor in a cascode arrangement. At least one transistor may be coupled between the seventh transistor and the eighth transistor in a cascode arrangement and at least one transistor may be coupled between the ninth transistor and the tenth transistor in a cascode arrangement. At least one transistor may also be coupled between the eleventh transistor and the twelfth transistor in a cascode arrangement.

A thirteenth transistor and a fourteenth transistor may be coupled between the first transistor and the second transistor, and the thirteenth transistor may be an NMOS transistor and the fourteenth transistor may be a PMOS transistor. The thirteenth transistor and the first transistor may be cascoded, and the second transistor and the fourteenth transistor may be coupled in a current mirror configuration. A fifteenth transistor and a sixteenth transistor may be coupled between the third transistor and the fourth transistor, and the fifteenth transistor may be an NMOS transistor and the sixteenth transistor may be a PMOS transistor. The fifteenth transistor and the third transistor may be cascoded, and the fourth transistor and the sixteenth transistor may also be coupled in a current mirror configuration.

A seventeenth transistor and an eighteenth transistor may be coupled between the fifth transistor and the sixth transistor, and the seventeenth transistor may be an NMOS transistor and the eighteenth transistor may be a PMOS transistor. The fifth transistor and the eighteenth transistor may be cascoded, and sixth transistor and the seventeenth transistor may be coupled in a current mirror configuration. A nineteenth transistor and a twentieth transistor may be coupled between the seventh transistor and the eighth transistor, and the nineteenth transistor may be an NMOS transistor and the twentieth transistor may be a PMOS transistor. The nineteenth transistor and the seventh transistor may be cascoded, and the eighth transistor and the twentieth transistor may also be cascoded.

A twenty-first transistor and a twenty-second transistor may be coupled between the ninth transistor and the tenth transistor, and the twenty-first transistor may be an NMOS transistor and the twenty-second transistor may be a PMOS transistor. The ninth transistor and the twenty-second transistor may be cascoded, and the tenth transistor and the twenty-first transistor may also be coupled in a current mirror configuration. A twenty-third transistor and a twenty-fourth transistor coupled between the eleventh transistor and the twelfth transistor, and the twenty-third transistor may be an NMOS and the twenty-fourth transistor may be a PMOS. The twelfth transistor and the twenty-fourth transistor may be cascoded, and the twenty-third transistor and the eleventh transistor may be cascoded.

These and other advantages, aspects and novel features of the present invention, as well as details of an illustrated embodiment thereof, will be more fully understood from the following description and drawings.

BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is a block diagram of an exemplary system for a fully differential amplifier output stage, in accordance with an embodiment of the invention.

FIG. 2 is a block diagram illustrating the fully differential amplifier output stage of FIG. 1 with cascoded devices for voltage standoff, in accordance with an embodiment of the invention.

FIG. 3 is a block diagram illustrating the fully differential amplifier output stage of FIG. 1 without cascoded devices, in accordance with an embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

Certain embodiments of the invention may be found in a method and apparatus for a fully differential amplifier output stage. In accordance with an embodiment of the invention, the fully differential amplifier output stage may comprise an input stage and two output stages. The input stage, which may also be referred to as a differential input stage, may be adapted to receive differential input signals (in and inb) and generate two differential output signals (out and outb) at the output stages.

The differential input stage may be configured in a differential pair configuration with a tail current. The tail current may be divided between two legs of the input stage and may be higher in the leg that may have the higher of the two input voltage levels of in or inb. In accordance with an aspect of the invention, the devices in each leg of the fully differential amplifier output stage may be cascoded to avoid electrical voltage overstress. The top device in each leg of the differential input stage may be coupled in a diode configuration and may be utilized to mirror the current into another NMOS current mirror as well as to a PMOS output device. The gates of the PMOS output devices may be connected in a cross-coupled configuration. The NMOS current mirrors may be utilized to mirror the current into the NMOS output devices in a non-cross-coupled configuration. Since there may be a longer delay to the NMOS output devices due to the additional mirroring stage, resistors may be utilized between the P-diodes of the differential input stage and the gates of the PMOS output devices. This may create an RC time constant that may delay the turn-on time of the PMOS output devices which may provide improved propagation delay matching.

FIG. 1 is a block diagram of an exemplary system for a fully differential amplifier output stage in accordance with an embodiment of the invention. Referring to FIG. 1, the amplifier comprises an input stage 104, a first output stage 102 and a second output stage 106. Transistors m3, m4, m5, m6 in the first output stage 102 may be PMOS transistors and transistors m1, m2, m7, m8 in the first output stage may be NMOS transistors. In the second output stage 106, transistors m18, m19, m24, m25 may be PMOS transistors and transistors m20, m21, m22, m23 may be NMOS transistors. In the differential input stage 104, transistors m9, m10, m16, and m17 may be PMOS transistors and transistors m11, m12, m13, m14, m15 may be NMOS transistors.

The source of each of transistors m4, m5, m9, m17, m18, m25 may be tied to, for example, a 3.3 v source. The source of each of transistors m1, m8, m13, m21 and m22 may be tied to ground. Transistors m9 and m17 in the differential input stage may function as diode current mirrors that may mirror the current from a corresponding leg of the input stage 104 over to a corresponding leg of each of the output stages 102, 106. Transistor m8 in the first output stage 102 functions as a diode current mirror and transistor m21 in the second output stage 106 also functions as a diode current mirror. Transistor m13 may be configured as the current source for the differential input stage.

In instances when input signal “in” may be greater than input signal “inb,” then current flows through transistors m12, m11, m10, and m9. Throughout this disclosure, whenever a first signal is described as being greater than a second signal, this means that the first signal is sufficiently high enough to steer a current in a leg of the amplifier that is associated with the first signal. Since the gates of transistor m5 and m9 may be coupled, current may be mirrored from transistor m9, which may be configured as a current mirror, to transistor m5 and flows through transistors m6, m7 and m8. Since the current in transistor m8 may be mirrored to transistor m1, current may flow through transistor m1 and transistor m2 thereby pulling the output “outb” low. Since input “in” may be greater than input “inb,” then there may be negligible current in transistors m14, m15, m16, and m17 of the right leg of the differential input stage 104. Also, since the gate of transistor m17 may be mirrored to transistor m4 via coupling 108, minimal current may flow in transistors m4 and m3.

Since the gate of transistor m17 may be mirrored to transistor m18, a minimal current may flow through transistors m18, m19, m20, and m21. Furthermore since the gates of transistors m21 and m22 may be coupled, a minimal current may be mirrored from transistor m21, which may be configured as a current mirror, to transistor m22. Therefore, a minimal amount of current may flow through transistor m23. Transistor m9 may mirror current to transistor m25, and the mirrored current may flow through transistors m25 and m24, thereby pulling the output “out” high.

In instances when input signal “inb” is greater than input signal “in,” then current may flow through transistors m14, m15, m16, and m17. Since the gates of transistor m17 and m18 may be coupled, current may be mirrored from transistor m17, which may be configured as a current mirror, to transistor m18 and may flow through transistors m19, m20 and m21. Since the current in transistor m21 may be mirrored over to transistor m22, current may flow through transistor m22 and transistor m23, thereby pulling output “out” low. Since input “inb” is greater than input “in,” then there may be negligible current in transistors m12, m11, m10, and m9 of the left leg of the differential input stage 104. Also, since the output of transistor m9 may be mirrored to transistor m25 via coupling 110, minimal current may flow in transistor m25 and transistor m24.

Since the gate of transistor m9 may be mirrored to transistor m5, a minimal current may flow through transistors m5, m6, m7, and m8. Furthermore, since the gates of transistors m8 and m1 may be coupled, a minimal current may be mirrored from transistor m8, which may be configured as a current mirror, to transistor m1. Therefore, a minimal amount of current may flow through transistor m2. Transistor m17 may mirror current to transistor m4, and the mirrored current may flow through transistors m4 and m3, thereby pulling the output “outb” high.

In accordance with an embodiment of the invention, with reference to FIG. 1, the fully differential amplifier output stage may comprise input stage 104 and two output stages 102 and 106. The differential input stage 104 may be adapted to receive differential input signals “in” and “inb” and generate two differential output signals “out” and “outb” at the output stages. The differential input stage 104 may be configured in a differential pair configuration with a tail current generated by transistor m13. In this regard, transistor m13 may be a current source. The tail current that may be generated by the transistor m13 may be divided between a left leg and a right leg of the input stage 104 and may be higher in the leg that may have the higher of the two input voltage levels (in or inb). For example, if input “in” is logic 1 and input “inb” is logic 0, then a majority of current will flow in the left leg of the differential input stage 104. However, if the input “inb” is logic 1 and input “in” is logic 0, then a majority of current may flow in the right leg of the differential input stage 104.

In accordance with an aspect of the invention, the transistors in each leg of the fully differential amplifier stages 102, 104, 106 may be cascoded to avoid electrical voltage overstress. The top device in each leg of the differential input stage 104 may be coupled in a diode configuration and may be utilized to mirror the current into another NMOS current mirror as well as to a PMOS output device. The gate of the PMOS output devices may be connected in a cross-coupled configuration. The NMOS current mirrors may be utilized to mirror the current into the NMOS output devices in a non-cross-coupled configuration.

In the fully differential amplifier output stage of FIG. 1, the transistors may be cascoded to ensure that 3.3 v may not be seen at the junctions of the devices. For example, in the first output stage 102, transistors m2, m3, m6, and m7 are cascoded to ensure voltage standoff. Similarly, transistors m10, m11, m15 and m16 in the differential input stage 104 and transistors m19, m20, m23 and m24 are cascoded to ensure voltage standoff in the second output stage 106. Accordingly, it should be recognized that the transistors m2, m3, m6, m7 m10, m11, m15, m16, m19, m20, m23, and m24 may be eliminated if the appropriate voltage may be applied without departing from the various aspects of the invention. FIG. 3 illustrates an embodiment of the invention without cascoded devices.

FIG. 2 is a block diagram illustrating the fully differential amplifier output stage of FIG. 1 with cascoded devices for voltage standoff, in accordance with an embodiment of the invention. Referring to FIG. 2, there is shown a differential input stage 204, a first output stage 202 and a second output stage 206. The differential input stage 204 comprises a left leg, a right leg and a current source m328. The left leg of the differential input stage 204 comprises transistors m19, m327, m325, m9 and the right leg of the differential input stage 204 comprises transistors m269, m326, m324 and m25. The inputs to the differential input stage 204 may be “in” which may be coupled to transistor m19 and “inb” which may be coupled to transistor m269. In the differential input stage 204, transistors m325 and m9 function as a diode current mirror and transistors m324 and m25 also function as a diode current mirror.

The first output stage 202 may comprise a left leg and a right leg. The left leg of the first output stage 202 may comprise transistors m287, m296, m282, m283 and the right leg of the first output stage 202 may comprise transistors m302, m320, m322, and m28. In the first output stage 202, transistors m320 and m302 may function as a diode current mirror.

The second output stage 206 may comprise a left leg and a right leg. The left leg of the second output stage 206 may comprise transistors m279, m321, m323, m5 and the right leg of the second output stage 206 may comprise transistors m185, m174, m122, and m121. In the second output stage 206, transistors m321 and m279 may function as a diode current mirror.

In operation, if the input “in” is greater than “inb”, then transistor m328 may sink current through the left leg of the differential input stage 204 through transistors m19, m327, m325, and m9. The current from transistor m9 may be mirrored to transistor m28 and may flow through transistors m322, m320 and m302. The current from transistor m302 may be mirrored to transistor m287 and may flow through transistor m296 to the output “outb.” Since transistor m283 may be turned off, output “outb” may be pulled low. Since the input “in” is greater than “inb”, then there may be minimal current in transistors m269, m326, m324 and m25 of the right leg of the differential input stage 204. Also, since the gate of the transistor m25 may be mirrored to transistor m283 via coupling 208, then minimal current may flow in transistors m283 and transistor m282.

Since the gate of transistor m25 may be mirrored to transistor m5, a minimal current may flow through transistors m5, m323, m321, and m279. Furthermore since the gates of transistors m279 and m185 may be coupled, a minimal current may be mirrored from transistor m279, which may be configured as a current mirror, to transistor m185. Therefore, a minimal amount of current may flow through transistor m174. Transistor m9 may mirror current to transistor m121, and the mirrored current may flow through transistors m121 and m122, thereby pulling the output pad “out” high.

FIG. 2 further comprises a plurality of transistors, namely m303, m304, m305 and m306 that may be utilized to mitigate the effects of a leakage current due to a mismatch in the transistors. The gates of each of the transistors m303, m304, m305 and m306 may be controlled by logic which turns these transistors on and off based on the differential input signals “in” and “inb.” In the case where input “in” is greater than input “inb” and current may be mirrored in the left leg resulting in pad “outb” being pulled low, transistor m306 may be turned on to pull the gate of transistor m283 high in order to make sure that there may be minimal current flowing in transistors m283 and m282. Simultaneously, transistor m303 may be off. Similarly, for this case, output “out” may be pulled high and transistor m304 may be turned on to pull the gate of transistor m185 low in order to ensure that there may be minimal current flowing in transistors m185 and m174. Simultaneously, transistor m305 may be off.

In the case where input “inb” is greater than input “in” and current may be mirrored in the right leg resulting in pad “out” being pulled low, transistor m305 may be turned on to pull the gate of transistor m121 high in order to make sure that there may be no current flowing in transistors m121 and m122. Simultaneously, transistor m304 may be off. Similarly, for this case, output “outb” may be pulled high and transistor m303 may be turned on to pull the gate of transistor m287 low in order to ensure that there may be minimal current flowing in transistors m287 and m296. Simultaneously, transistor m306 may be off.

In operation, if the input “inb” is greater than “in”, then transistor m328 may sink current via coupling R12 through the right leg of the differential input stage 204 through transistors m269, m326, m324, and m25. The current from transistor m25 may be mirrored to transistor m5 and flows through transistors m5, m323, m321 and m279. The current from transistor m279 may be mirrored to transistor m185 and may flow through transistor m174 to the output pad “out.” Since transistor m121 may be turned off, output “out” may be pulled low. Since the input “inb” is greater than “in”, then there may be negligible current in transistors m19, m327, m325 and m9 of the left leg of the differential input stage 204. Also, since the gate of transistor m9 may be mirrored to transistor m121 via coupling R10, then minimal current may flow in transistors m121 and m122.

In operation, if the input “in” is greater than “inb”, then transistor m328 may sink current via coupling R12 through the left leg of the differential input stage 204 through transistors m19, m327, m325, and m9. The current from transistor m9 may be mirrored to transistor m28 and may flow through transistors m28, m322, m320 and m302. The current from transistor m302 may be mirrored to transistor m287 and may flow through transistor m296 to the output “outb.” Since transistor m283 may be turned off, output “outb” may be pulled low. Since the input “in” is greater than “inb”, then there may be negligible current in transistors m269, m326, m324 and m25 of the right leg of the differential input stage 204. Also, since the gate of transistor m25 may be mirrored to transistor m283 via coupling R11, then minimal current may flow in transistors m283 and m282.

FIG. 3 is a block diagram illustrating the fully differential amplifier output stage of FIG. 1 without cascoded devices, in accordance with an embodiment of the invention. Referring to FIG. 3, there is shown a differential input stage 304, a first output stage 302 and a second output stage 306. The differential input stage 304 may comprise a left leg, a right leg and a current source transistor m8. The left leg of the differential input stage 304 may comprise transistors m11, m22, and the right leg of the differential input stage 304 may comprise transistors m7, and m21. The inputs to the differential input stage 304 may be “in” which may be coupled to a gate of transistor m11 and “inb” which may be coupled to a gate of transistor m7. In the differential input stage 304, transistor m22 may function as a diode current mirror and transistor m21 also may function as a diode current mirror.

The first output stage 302 may comprise a left leg and a right leg. The left leg of the first output stage 302 may comprise transistors m30, m3 and the right leg of the first output stage 302 may comprise transistors m23 and m10. In the first output stage 302, transistor m10 may function as a diode current mirror that mirrors current from transistor m23 to transistor m3.

The second output stage 306 may comprise a left leg and a right leg. The left leg of the second output stage 306 may comprise transistors m20, m13 and the right leg of the second output stage 306 may comprise transistors m24 and m4. In the second output stage 306, transistor m13 may function as a diode current mirror that mirrors current from transistor m20 to transistor m4.

In operation, if the input “in” is greater than “inb”, then transistor m8 may sink current via coupling R1 through the left leg of the differential input stage 304 through transistors m11, and m22. The current from transistor m11 may be mirrored to transistor m23 and may flow through transistor m10. The current from transistor m10 may be mirrored to transistor m3 and may flow through transistor m3 to the output pad “outb.” Since transistor m30 may be turned off, “outb” may be pulled low. Since the input “in” is greater than the input “inb”, then there may be minimal current in transistors m7 and m21 of the right leg of the differential input stage 304. Also, since the current of transistor m21 may be mirrored to transistor m30 via coupling 308, then minimal current may flow in transistor m30.

Since the current of transistor m21 may be mirrored to transistor m20, a minimal current will flow through transistors m20 and m13. Furthermore since the gates of transistors m13 and m4 may be coupled, a minimal current may be mirrored from transistor m13, which may be configured as a current mirror, to transistor m4. Since transistor m22 may mirror current to transistor m24 via coupling 310, the mirrored current may flow through transistor m24, thereby pulling the output pad “out” high.

In operation, if the input “inb” is greater than “in”, then transistor m8 may sink current via coupling R1 through the right leg of the differential input stage 304 through transistors m7 and m21. The current from transistor m21 may be mirrored to transistor m20 and may flow through transistor m13. The current from transistor m13 may be mirrored to transistor m4 and may flow through transistor m4 to the output “out.” Since transistor m24 may be turned off, “out” pulls low. Since the input “inb” is greater than “in”, then there may be minimal current in transistors m11 and m22 of the left leg of the differential input stage 304. Also, since the current of the transistor m22 may be mirrored to transistor m24 via coupling 310, then minimal current may flow in transistor m24.

Since the current of transistor m22 may be mirrored to transistor m23, a minimal current will flow through transistors m23 and m10. Furthermore since the gates of transistors m10 and m3 may be coupled, a minimal current may be mirrored from transistor m10, which may be configured as a current mirror, to transistor m3. Since transistor m21 may mirror current to transistor m30 via coupling 308, the mirrored current may flow through transistor m30, thereby pulling the output “outb” high.

In accordance with an embodiment of the invention, the invention may be implemented in a completely complementary fashion by replacing the NMOS transistors with PMOS transistors and the PMOS transistors with NMOS transistors, and reversing the power and ground connections. In this regard, transistors m3, m4, m5, m6 in the first output stage 102 may be NMOS transistors and transistors m1, m2, m7, m8 in the first output stage 102 may be PMOS transistors. In the second output stage 106, transistors m18, m19, m24, m25 may be NMOS transistors and transistors m20, m21, m22, m23 may be PMOS transistors. In the differential input stage 104, transistors m9, m10, m16, and m17 may be NMOS transistors and transistors m11, m12, m13, m14, m15 may be PMOS transistors. Additionally, there are also variations of the input stage that may be implemented, which may include, but is not limited to, a fully complementary (NMOS and PMOS) differential input stage. Although not shown, diodes may be added to the output to mitigate the effects of electrostatic discharge (ESD). For example, in FIG. 3, one or more diodes may be coupled to the outputs “out” and “outb.” The arrangement of FIGS. 1-3 may also be implemented utilizing bipolar technology. It should also be recognized by one skilled in the art that other type of current mirrors may also be utilized without departing from the various aspects of the invention.

With reference to FIG. 1, when input signal “in” is high, as soon as transistor m9 starts mirroring the current, transistor m25 will start pulling the output signal “out” high. Additional time may be required for the current to be mirrored from transistor m9 to transistor m5 and the current from transistor m5 to be mirrored by transistor m8 to transistor m1. Since there may be additional delay for the current to be mirrored from transistor m9 to transistor m5 to transistor m8 to transistor m1 to the output “outb,” a resistor may be added to path 110 to compensate for this propagation delay by introducing a RC delay to delay the turning on of transistor m25. Accordingly, FIG. 3, for example, illustrates a resistor R2 in path 310, which provides compensation for the propagation delay when current may be mirrored from m22 to m23 to m10 to m3 to the output “outb.” In this regard, the resistor R2 may delay the turning on of transistor m24.

Similarly, with reference to FIG. 1, in the second output stage 106, additional time may be required for the current to be mirrored from transistor m117 to transistor m18 and the current from transistor m18 to be mirrored by transistor m21 to transistor m22. Since there may be additional delay for the current to be mirrored from transistor m17 to transistor m18 to transistor m21 to transistor m22 to the output “out,” a resistor may be added to path 108 to compensate for this propagation delay by introducing a RC delay to delay the turning of transistor m4. Accordingly, FIG. 3, for example, illustrates a resistor R3 in path 308, which may provide compensation for the propagation delay when current may be mirrored from m21 to m20 to m13 to m4 to the output “out.” In this regard, the resistor R3 may delay the turning on of transistor m30.

Referring to FIG. 1, in instances where the input signal “in” is greater than its complement “inb” and there may be a minimal current flowing through transistors m14, m15, m16, and m17, and the minimal amount of current flowing may cause the gate of the transistor m17 to bias to the point where it may start to conduct in order to supply the leakage current. Accordingly, if there is a mismatch between transistor m17, and transistors m18 and m4, then transistor m17 may potentially mirror a significant amount of current to transistors m18 and m4. To prevent this potential mirroring of a significant amount of current, the gate of transistor m17 may need to be pulled up to the 3.3 v supply in order to ensure that transistors m17, m18 and m4 may be off. Accordingly, in FIG. 2, for example, transistors m303, m304, m305, and m306 ensure that there may be no leakage current by shutting off the transistors.

Accordingly, the present invention may be realized in hardware, software, or a combination of hardware and software. The present invention may be realized in a centralized fashion in at least one computer system, or in a distributed fashion where different elements are spread across several interconnected computer systems. Any kind of computer system or other apparatus adapted for carrying out the methods described herein is suited. A typical combination of hardware and software may be a general-purpose computer system with a computer program that, when being loaded and executed, controls the computer system such that it carries out the methods described herein.

The present invention may also be embedded in a computer program product, which comprises all the features enabling the implementation of the methods described herein, and which when loaded in a computer system is able to carry out these methods. Computer program in the present context means any expression, in any language, code or notation, of a set of instructions intended to cause a system having an information processing capability to perform a particular function either directly or after either or both of the following: a) conversion to another language, code or notation; b) reproduction in a different material form.

While the present invention has been described with reference to certain embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the present invention without departing from its scope. Therefore, it is intended that the present invention not be limited to the particular embodiment disclosed, but that the present invention will include all embodiments falling within the scope of the appended claims. 

1. A transistor circuit, comprising: an input stage, said input stage comprising: a first current source coupled to a first transistor; a second transistor coupled to said first transistor, wherein said second transistor is configured as a current mirror; a third transistor coupled to said first current source; and a fourth transistor coupled to said third transistor, wherein said fourth transistor is configured as a current mirror; a first output stage, said first output stage comprising: a fifth transistor coupled to said second transistor; a sixth transistor coupled to said fifth transistor, wherein said sixth transistor is configured as a current mirror; a seventh transistor coupled to said sixth transistor; and an eighth transistor coupled to said seventh transistor; a second output stage, said second output stage comprising: a ninth transistor coupled to said fourth transistor; a tenth transistor coupled to said ninth transistor, wherein said tenth transistor is configured as a current mirror; an eleventh transistor coupled to said tenth transistor; and a twelfth transistor coupled to said eleventh transistor; a first input, wherein said first input is coupled to a gate of said first transistor; a second input, wherein said second input is coupled to a gate of said third transistor; a first output, wherein said first output is coupled to a drain of said twelfth transistor and a drain of said eleventh transistor; and a second output, wherein said second output is coupled to a drain of said eighth transistor and to a drain of said seventh transistor; and wherein said second transistor is coupled to said twelfth transistor and said fourth transistor is coupled to said eighth transistor.
 2. The system according to claim 1, wherein said first input and said second input are complementary.
 3. The system according to claim 1, wherein said first output and said second output are complementary.
 4. The system according to claim 1, further comprising an external power source, wherein a higher voltage potential of said external power source is coupled to a source of each of said second transistor, said fourth transistor, said fifth transistor, said eighth transistor, said ninth transistor, and said twelfth transistor, wherein said second transistor, said fourth transistor, said fifth transistor, said eighth transistor, said ninth transistor, and said twelfth transistor are PMOS.
 5. The system according to claim 1, further comprising an external power source, wherein a lower voltage potential of said external power source is coupled to a source of each of said sixth transistor, said seventh transistor, said tenth transistor, said eleventh transistor and said first current source, wherein said first transistor, said third transistor, said sixth transistor, said seventh transistor, said tenth transistor, said eleventh transistor and said first current source are NMOS.
 6. The system according to claim 1, wherein a drain of said first current source is coupled to a source of said first transistor and to a source of said third transistor.
 7. The system according to claim 1, further comprising a first resistive device, wherein a first terminal of said first resistive device is coupled to a drain of said first current source and a second terminal of said first resistive device is coupled to a source of said first transistor and to a source of said third transistor.
 8. The system according to claim 1, wherein a gate of said second transistor is coupled to a drain of said second transistor, to a drain of said first transistor, to a gate of said fifth transistor, and to a gate of said twelfth transistor.
 9. The system according to claim 1, further comprising a second resistive device, wherein a first terminal of said second resistive device is coupled to a gate of said second transistor, to a drain of said second transistor, to a drain of said first transistor, and to a gate of said fifth transistor, wherein a second terminal of said second resistive device is coupled to a gate of said twelfth transistor.
 10. The system according to claim 1, wherein a gate of said fourth transistor is coupled to a drain of said fourth transistor, to a drain of said third transistor, to a gate of said ninth transistor, and to a gate of said eighth transistor.
 11. The system according to claim 1, further comprising a third resistive device, wherein a first terminal of said third resistive device is coupled to a gate of said fourth transistor, to a drain of said fourth transistor, to a drain of said third transistor, and to a gate of said ninth transistor wherein said second terminal of said third resistive device is coupled to a gate of said eighth transistor.
 12. The system according to claim 1, wherein a gate of said sixth transistor is coupled to a drain of said sixth transistor, to a drain of said fifth transistor, and to a gate of said seventh transistor.
 13. The system according to claim 1, wherein a gate of said tenth transistor is coupled to a drain of said tenth transistor, to a drain of said ninth transistor, and to a gate of said eleventh transistor.
 14. The system according to claim 1, further comprising a first pull-down device, wherein said first pull-down device is coupled to said sixth transistor and said seventh transistor.
 15. The system according to claim 14, further comprising an external power source, wherein a lower voltage potential of said external power source is coupled to a source of said first pull-down device, wherein a drain of said first pull-down device is coupled to a gate of said sixth transistor and to a gate of said seventh transistor and said first pull-down device is NMOS.
 16. The system according to claim 1, further comprising a second pull-down device, wherein said second pull-down device is coupled to said tenth transistor and to said eleventh transistor.
 17. The system according to claim 16, further comprising an external power source, wherein a lower voltage potential of said external power source is coupled to a source of said second pull-down device, wherein a drain of said second pull-down device is coupled to a gate of said tenth transistor and to a gate of said eleventh transistor and said second pull-down device is NMOS.
 18. The system according to claim 1, further comprising a first pull-up device, wherein said first pull-up device is coupled to said fourth transistor, said eighth transistor and said ninth transistor.
 19. The system according to claim 18, further comprising an external power source, wherein a higher voltage potential of said external power source is coupled to a source of said first pull-up device, wherein a drain of said first pull-up device is coupled to a gate of said fourth transistor, to a drain of said fourth transistor, to a gate of said eighth transistor and to a gate of said ninth transistor and said first pull-up device is PMOS.
 20. The system according to claim 18, further comprising an external power source, wherein a higher voltage potential of said external power source is coupled to a source of said first pull-up device, wherein a drain of said first pull-up device is coupled to a gate of said eighth transistor and to a first terminal of a third resistive device, and a second terminal of said third resistive device is coupled to a gate of said fourth transistor, to a drain of said fourth transistor and to a gate of said ninth transistor and said first pull-up device is PMOS.
 21. The system according to claim 1, further comprising a second pull-up device, wherein said second pull-up device is coupled to said second transistor, to said fifth transistor and to said twelfth transistor.
 22. The system according to claim 21, further comprising an external power source, wherein a higher voltage potential of said external power source is coupled to a source of said second pull-up device, wherein a drain of said second pull-up device is coupled to a gate of said second transistor, to a drain of said second transistor, to a gate of said fifth transistor and to a gate of said twelfth transistor and said second pull-up device is PMOS.
 23. The system according to claim 21, further comprising an external power source, wherein a higher voltage potential of said external power source is coupled to a source of said second pull-up device wherein a drain of said second pull-up device is coupled to a gate of said twelfth transistor and to a first terminal of a second resistive device, a second terminal of said second resistive device is coupled to a gate of said second transistor, to a drain of said second transistor and to a gate of said fifth transistor wherein said second pull-up device is PMOS.
 24. The system according to claim 1, further comprising at least one transistor coupled between said first transistor and said second transistor in a cascode arrangement.
 25. The system according to claim 1, further comprising at least one transistor coupled between said third transistor and said fourth transistor in a cascode arrangement.
 26. The system according to claim 1, further comprising at least one transistor coupled between said fifth transistor and said sixth transistor in a cascode arrangement.
 27. The system according to claim 1, further comprising at least one transistor coupled between said seventh transistor and said eighth transistor in a cascode arrangement.
 28. The system according to claim 1, further comprising at least one transistor coupled between said ninth transistor and said tenth transistor in a cascode arrangement.
 29. The system according to claim 1, further comprising at least one transistor coupled between said eleventh transistor and said twelfth transistor in a cascode arrangement.
 30. The system according to claim 1, further comprising a thirteenth transistor and a fourteenth transistor coupled between said first transistor and said second transistor, wherein said thirteenth transistor is NMOS and said fourteenth transistor is PMOS, and said thirteenth transistor and said first transistor are cascoded, and said second transistor and said fourteenth transistor are coupled in a current mirror configuration.
 31. The system according to claim 1, further comprising a fifteenth transistor and a sixteenth transistor coupled between said third transistor and said fourth transistor, wherein said fifteenth transistor is NMOS and said sixteenth transistor is PMOS, and said fifteenth transistor and said third transistor are cascoded, and said fourth transistor and said sixteenth transistor are coupled in a current mirror configuration.
 32. The system according to claim 1, further comprising a seventeenth transistor and an eighteenth transistor coupled between said fifth transistor and said sixth transistor, wherein said seventeenth transistor is NMOS and said eighteenth transistor is PMOS, said fifth transistor and said eighteenth transistor are cascoded, and said sixth transistor and said seventeenth transistor are coupled in a current mirror configuration.
 33. The system according to claim 1, further comprising a nineteenth transistor and a twentieth transistor coupled between said seventh transistor and said eighth transistor, wherein said nineteenth transistor is NMOS and said twentieth transistor is PMOS and said nineteenth transistor and said seventh transistor are cascoded and said eighth transistor and said twentieth transistor are cascoded.
 34. The system according to claim 1, further comprising a twenty-first transistor and a twenty-second transistor coupled between said ninth transistor and said tenth transistor, wherein said twenty-first transistor is NMOS and said twenty-second transistor is PMOS, and wherein said ninth transistor and said twenty-second transistor are cascoded, and said tenth transistor and said twenty-first transistor are coupled in a current mirror configuration.
 35. The system according to claim 1, further comprising a twenty-third transistor and a twenty-fourth transistor coupled between said eleventh transistor and said twelfth transistor, wherein said twenty-third transistor is NMOS and said twenty-fourth transistor is PMOS, and said twelfth transistor and said twenty-fourth transistor are cascoded, and said twenty-third transistor and said eleventh transistor are cascoded.
 36. A method for implementing a transistor circuit, comprising: coupling a differential input stage to a first differential output stage and to a second differential output stage, wherein for said differential input stage: coupling a first current source to a first transistor; coupling a second transistor to said first transistor, wherein said second transistor is configured as a current mirror; coupling a third transistor to said first current source; and coupling a fourth transistor to said third transistor, wherein said fourth transistor is configured as a current mirror; wherein for said first differential output stage: coupling a fifth transistor to said second transistor; coupling a sixth transistor to said fifth transistor, wherein said sixth transistor is configured as a current mirror; coupling a seventh transistor to said sixth transistor; and coupling an eighth transistor to said seventh transistor; wherein for said second differential output stage: coupling a ninth transistor to said fourth transistor; coupling a tenth transistor to said ninth transistor, wherein said tenth transistor is configured as a current mirror; coupling an eleventh transistor to said tenth transistor; and coupling a twelfth transistor to said eleventh transistor; coupling said second transistor to said twelfth transistor; coupling said fourth transistor to said eighth transistor; coupling a first input to a gate of said first transistor; coupling a second input to a gate of said third transistor; coupling a first output to a drain of said twelfth transistor and a drain of said eleventh transistor; and coupling a second output to a drain of said eighth transistor and to a drain of said seventh transistor.
 37. The method according to claim 36, wherein said first input and said second input are complementary.
 38. The method according to claim 36, wherein said first output and said second output are complementary.
 39. The method according to claim 36, further comprising coupling a higher voltage potential of an external power source to a source of each of said second transistor, said fourth transistor, said fifth transistor, said eighth transistor, said ninth transistor, and said twelfth transistor, wherein said second transistor, said fourth transistor, said fifth transistor, said eighth transistor, said ninth transistor, and said twelfth transistor are PMOS.
 40. The method according to claim 36, further comprising coupling a lower voltage potential of an external power source to a source of each of said sixth transistor, said seventh transistor, said tenth transistor, said eleventh transistor and said first current source, wherein said first transistor, said third transistor, said sixth transistor, said seventh transistor, said tenth transistor, said eleventh transistor and said first current source are NMOS.
 41. The method according to claim 36, further comprising coupling a drain of said first current source to a source of said first transistor and to a source of said third transistor.
 42. The method according to claim 36, further comprising: coupling a first terminal of a first resistive device to a drain of said first current source; and coupling a second terminal of said first resistive device to a source of said first transistor and to a source of said third transistor.
 43. The method according to claim 36, further comprising coupling a gate of said second transistor to a drain of said second transistor, to a drain of said first transistor, to a gate of said fifth transistor, and to a gate of said twelfth transistor.
 44. The method according to claim 36, further comprising: coupling a gate of said second transistor to a drain of said second transistor, to a drain of said first transistor, to a gate of said fifth transistor, and to a first terminal of a second resistive device; and coupling a second terminal of said second resistive device to a gate of said twelfth transistor.
 45. The method according to claim 36, further comprising coupling a gate of said fourth transistor to a drain of said fourth transistor, to a drain of said third transistor, to a gate of said ninth transistor, and to a gate of said eighth transistor.
 46. The method according to claim 36, further comprising: coupling a gate of said fourth transistor to a drain of said fourth transistor, to a drain of said third transistor, to a gate of said ninth transistor, and to a first terminal of a third resistive device; and coupling a second terminal of a third resistive device to a gate of said eighth transistor.
 47. The method according to claim 36, further comprising coupling a gate of said sixth transistor to a drain of said sixth transistor, to a drain of said fifth transistor, and to a gate of said seventh transistor.
 48. The method according to claim 36, further comprising coupling a gate of said tenth transistor to a drain of said tenth transistor, to a drain of said ninth transistor, and to a gate of said eleventh transistor.
 49. The method according to claim 36, further comprising coupling a first pull-down device to said sixth transistor and said seventh transistor.
 50. The method according to claim 49, further comprising: coupling a lower voltage potential of an external power source to a source of said first pull-down device; and coupling a drain of said first pull-down device to a gate of said sixth transistor and to a gate of said seventh transistor wherein said first pull-down device is NMOS.
 51. The method according to claim 36, further comprising coupling a second pull-down device to said tenth transistor and to said eleventh transistor.
 52. The method according to claim 51, further comprising: coupling a lower voltage potential of an external power source to a source of said second pull-down device; and coupling a drain of said second pull-down device to a gate of said tenth transistor and to a gate of said eleventh transistor wherein said second pull-down device is NMOS.
 53. The method according to claim 36, further comprising coupling a first pull-up device to said fourth transistor, said eighth transistor and said ninth transistor.
 54. The method according to claim 53, further comprising: coupling a higher voltage potential of an external power source to a source of said first pull-up device; and coupling a drain of said first pull-up device to a gate of said fourth transistor, to a drain of said fourth transistor, to a gate of said eighth transistor and to a gate of said ninth transistor, wherein said first pull-up device is PMOS.
 55. The method according to claim 53, further comprising: coupling a higher voltage potential of said external power source to a source of said first pull-up device; coupling a drain of said first pull-up device to a gate of said eighth transistor and to a first terminal of a third resistive device; and coupling a second terminal of said third resistive device to a gate of said fourth transistor, to a drain of said fourth transistor and to a gate of said ninth transistor, wherein said first pull-up device is PMOS.
 56. The method according to claim 36, further comprising coupling a second pull-up device to said second transistor, to said fifth transistor and to said twelfth transistor.
 57. The method according to claim 56, further comprising: coupling a higher voltage potential of an external power source to a source of said second pull-up device; and coupling a drain of said second pull-up device to a gate of said second transistor, to a drain of said second transistor, to a gate of said fifth transistor and to a gate of said twelfth transistor, wherein said second pull-up device is PMOS.
 58. The method according to claim 56, wherein: coupling a higher voltage potential of said external power source to a source of said second pull-up device; coupling a drain of said second pull-up device to a gate of said twelfth transistor and to a first terminal of a second resistive device; and coupling a second terminal of said second resistive device to a gate of said second transistor, to a drain of said second transistor and to a gate of said fifth transistor, wherein said second pull-up device is PMOS. 